1. Field of the Invention
The present invention relates to a method in which electroless plating is used for plating metals onto the surface of a material, specular body, powder, or other object having low electrical conductivity. The present invention also relates to an electroless plating method for forming copper wiring on a semiconductor wafer, and more particularly to an electroless plating method suitable for semiconductor wafers in which minute vias or trenches can be embedded without forming voids, seams, or other defects.
2. Description of the Related Art
Electroless plating, which is a method for forming metal films on a substrate devoid of electrical conductivity, is employed when, for example, printed wirings are formed on resin substrates. Common processes entail performing so-called activation, which is a process whereby palladium or another noble metal is deposited in advance as a catalyst on the substrate as part of an electroless plating pretreatment. Conventionally used methods include those in which the substrate is first treated with a hydrochloric aqueous solution of SnCl2 and is then immersed in an aqueous solution of PdCl2 to adsorb Pd; and those in which Pd is deposited on the surface with the use of a colloid solution containing Sn and Pd. These methods have numerous disadvantages, such as the use of highly toxic Sn and the complexity of the treatment processes. In view of this, methods based on the use of silane-coupling agents having the functional groups that form complexes with Pd and other noble metals have recently been proposed in order to cover surfaces with these noble metals as electroless plating catalysts (Japanese Patent Publication Nos. S59-52701, S60-181294, S61-194183, and H3-44149).
With some of the methods featuring the above-mentioned silane-coupling agents, however, the material of the object to be plated makes it difficult to obtain a strongly adhered and uniform deposit when the plating catalyst fixative and the plating catalyst are treated separately, that is, the noble metal ions serving as catalysts are deposited after the coupling agent has been adsorbed on the object. This is attributed to the fact that the coupling agent modifies the surface of the object or that the noble metal ions cannot be deposited with adequate efficiency. For similar reasons or because palladium exhibits inadequate catalytic activity, it is sometimes impossible to achieve uniform plating for some types of materials of the object to be plated or plating conditions in methods featuring mixed solutions of amino silane-coupling agents and palladium chloride. In particular, it is difficult to fix noble metal ions (catalyst) to semiconductor specular surfaces such as semiconductor substrates by employing conventional SnCl2-based treatment in order to form electroless deposits on these surfaces. Another catalytic solution by conventional technique is known (U.S. Pat. No. 4,986,848). The catalytic solution aims to prevent from hollowing phenomenon in printed circuit board layers. However, the solution essentially includes particular amine compounds, which is not need in the present invention. The catalytic solution also may include a silane coupling agent. When a silane coupling agent is used, the solution needs much excess palladium compound comparing to the amount of the silane coupling agent, that is costly undesirable.
Conventionally, aluminum has mainly been used as a wiring material in semiconductor wafer processing. Because of an increase in wiring integration, highly electrically conductive copper has recently replaced aluminum to prevent an increase in signal delay time. The damascene method is used to form copper wiring, and commonly in this process, a wiring pattern is formed on a silicon wafer, a barrier layer and a seed layer are then deposited by sputtering or CVD, a wiring pattern is embedded by electroplating, and excess precipitated copper is removed with CMP.
When LSI wiring is formed on the surface of a silicon or other semiconductor wafer, vias or trenches are formed for embedding copper wiring, and a barrier metal selected from titanium, tantalum, tungsten, nitrides thereof, and the like is deposited by sputtering, CVD, or the like to a thickness of about 0.01–0.1 μm in order to prevent copper from diffusing in the silicon on the surface of the wafer. Conventionally, this barrier metal layer is covered with a thin copper layer (a seed layer) by sputtering, CVD, or the like in the same manner as described above. A barrier metal, which generally exhibits high electrical resistance, is copper with low electrical resistance which is provided (thinly deposited) in advance, in order to avoid a considerable difference in current density produced between the center portion and the periphery of the contacts on the perimeter of the wafer in the subsequently electroplated copper.
As increasingly narrower LSI wiring patterns are designed and vias and trenches become correspondingly narrower, the above-described conventionally performed sputtering methods fail to provide adequate coverage for the seed layer on the inside walls of the vias and trenches, creating defects (voids and seams) during subsequent electroplating. Although coverage is improved with CVD, the very high cost is a problem.